USC Component of PICS Activities:
Computational Resources.
- Silicon Graphics Computational and Imaging Laboratory
- Intel Paragon A4
Code and algorithm development is performed on satellite intel Paragons,
which are located at PICS Groundwater member institutions and
were provided through associated PICS equipment grants.
Algorithms and simulator codes are formulated, optimized, and matured
on the satelitte systems before being migrated to the larger machines
at ORNL for large field scale studies. By combining the PICS equipment
grant with a generous university match, USC has procured a Paragon A4
with fifty-six i860-XP processing nodes (one compute i860 processor and
one message handling i860 processor per node), 3 mass storage RAID
arrays, and four i860 service nodes with Ethernet and HIPPI connections.
Software
includes full UNIX on each node, a parallel debugger with graphics
interface, C and Fortran compilers, and various software libraries for
solving mathematically based problems such as large linear systems.
Peak performance is rated at 4.2 GFlops. For more information on
Intel hardware see
Intel Supercomputer Division. Additional sites for information on
developing code for the Paragon or for parallel computing in general,
include:
For more information on Supercomputing at USC and account information
please contact the system administrator Dr. Steve Johnson
(steve@isc.tamu.edu).
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